| Back |
Overview |
Why use PWM instead of a DAC?
The PWM is already available from the processor, and for this application delivers the equivalent of a 24 bit DAC. The control voltage to the OCXO varies very little over time and does not need the capabilities of a hardware DAC. Some other designs use PWM, and a few use dithering to give an output the equivalent of a 16 bit DAC. This is well short of what can be achieved - the PWM outputs bits at the processor clock rate, i.e. 10MHz. With suitable programming this can output between 0 and 10 million high bits per second which when averaged through a filter results in an average output of 0 to 5V in steps of 500nV. In this design the concept has been taken to the limit of the hardware by adjusting the PWM every 100µS and passing the resultant bit stream through a filter with a time constant of more than a second. The processor time required to do this is less than 25%, leaving plenty for other operations. The effect of a 500nV change in control voltage depends on the pulling range of the OXCO. For the MV89 it is less than 1/10 of a cycle per day.
Why not use a PLL?
In a way, this design does use a software/hardware PLL to track variations of the 1ppS (one pulse per second) signal from GPS module in 16nS increments. However the error term is not used to correct the control voltage directly, but is averaged in software over a long period. If the error term were used to 'correct' the OCXO its frequency will track short term variations in the 1ppS signal, which is not what is needed. Some designs use software to track the 1ppS to the resolution of the processor instruction time, which for the PIC is 4 clock cycles. This is quite coarse, and introduces some uncertainty in the OCXO frequency. Another approach uses a PLL using an intermediate frequency, such as the 40kHz available from some GPS units. With a very low pass filter this is a satisfactory solution but complex. The approach used here is to use a programmable delay line based on low cost chips, three resistors and two capacitors, and the capabilities of the microprocessor. The circuit as presented uses an external comparator but it is possible, but not tested, that the processor internal comparator would be adequate.
Temperature compensation
A problem noted by several constructors is drift due to variations in ambient temperature. There are several approaches - (1) avoid short term variations (2) design using components not affected by temperature (3) measure the variations and compensate for them in software. This design used the third approach. The disadvantage is that it requires patient measuring, a bit of guesswork, a bit of trail and error. The advantages are it is "free", and that it is not necessary to know what is causing the drift. It is however necessary to know the ambient temperature before any compensation can be applied. This circuit uses a thermistor to charge a capacitor and measures the time taken. Charging a capacitor is a necessary step for the programmable delay circuit, so the only added component is the thermistor. ATmega processors have a inbuilt temperature sensor so if the program were adapted for them, the thermistor would not be required.
Periodic rather than continuous variation of the control voltage
When using the device as a frequency reference, it is useful to have an idea of the actual frequency. If the control voltage is constant (ignoring any temperature compensation) and a correction is applied at the end of a period, the frequency can be estimated with some confidence. In this design, over the measurement period, the processor accumulates the delays in the delay circuit used to track the GPS signal. At the end of the period, two values are calculated - the average delay between the 1ppS signal and the OCXO, and the change in delay. The software does not correct frequency errors directly. There is a target delay and the software changes the control voltage to correct for deviations from the target by the end of the next measurement period. If the delay is on target for a whole period (i.e. on target at the beginning and end) then the frequency is correct. If the delay changes it means the frequency is not correct, and the correction results in a similar frequency error but in the opposite direction. This is necessary if the long term frequency is to be accurate. It follow that if the output frequency is used as a reference, and at the end of a period the change in delay is determined, the actual reference frequency can be calculated.
The Pusle Width Modulator
The resolution of the voltage created by the PWM is a function of how quickly the voltage needs to be changed. For this application, this can be many seconds without affecting performance. The PWM hardware puts out pulses, the duration of each pulse is determined by a timer (TMR2). The program sets this to 250 instruction cycles (1000 clock cycles, 100µS). The output is held high for 0 to 1000 clock cycles and low for the remainder. To get a constant voltage, this output has to be filtered. The result is a voltage from 0 to Vcc (5V). If the PWM value was varied occasionally, this voltage could only be varied in 1000 steps, too coarse for what is needed. The solution is to dither the PWM around the desired value. For instance, if the desired voltage is 1/3 of a volt, a constant PWM of 66 results in an output of 0.33V, and 67 results in 0.335V - close to 1/3V but not exact. But if the PWM were fed the repeating sequence 66, 66, 67 the average would be 1/3V. The penalty is that dithering creates short term variations in the output and these have to be filtered as well. The circuit uses extreme (probably excessive) filtering to remove all PWM and dithering artifacts. The program uses a 24 bit (3 byte) number to hold the target voltage and reloads the PWM every 100µS. The 24 bits are split into the most significant 10 bits and least significant 14 bits. Each 100µS the 14 bits are added to a software accumulator. If the accumulator overflows the PWM pulse width is set to 1 more than the 10 bit value; if there is no overflow the 10 bit value is loaded unchanged. The result is a stream of 15,000,000 bits over 1.5 seconds setting the average voltage within 1/3 µV of the desired value. This is much finer than required, removing the PWM as a source of uncertainty.
The Programmable time delay
This is a simple circuit inserted between the 1ppS source and the processor. The 1ppS is used to charge an RC (resistor/capacitor) network, and a comparator detects when the capacitor reaches a defined voltage. The time to charge depends on the charge on the capacitor before the 1ppS arrives. If the initial charge is close to the comparator threshhold, the time is short. If the initial charge is small, the time is longer. The processor has control over the charge, and can vary it so the delay changes in 16nS steps. This is described in detail elsewhere.
The delay circuit is used in two modes - fixed and variable. Fixed mode is used during initialisation when the frequency of the OCXO is tracked by varying the counter used to count instruction times between GPS pulses. This can handle large deviations from lock. Initialisation routines bring the the OCXO near to locking but once the frequency is close, counting instruction times is insensitive. For example a drift of 1 part in 10^8 takes up to 40 seconds to be detected. So when the OCXO is close to lock, the program deliberately detunes it by an estimated 1 part in 10^8 above and below the estimated lock frequency to determine the control voltage sensitivity (pulling). Once pulling sensitivity is known, variable delay mode is enabled and the delay step size can be measured (this circuit measured as approximately 16nS). Knowing the pulling sensitivity and the step size, the processor is able to measure the GPS/OCXO variations in terms of step size, and apply an appropriate change to the control voltage when required.
Once initialisation is complete, the program uses only variable mode. For convenience a 1 byte variable is used to track the delay, and the program uses the mid point of this variable (i.e. about 128) as a target delay. If the GPS pulse arrives early, the delay is decreased next pulse. If it arrives late, the delay is increased. Normally over a period of minutes the variable will move a few counts up and down due to jitter in the GPS pulse and/or noise in the circuit. The 1ppS from consumer grade GPS modules is generated on the clock of the GPS processor, and as this is not locked to the GPS signals it naturally jitters around the correct value due to quantization jitter (often called sawtooth error). Theoretically, the program can track differences using byte values from 0 to 255, which corresponds to around +- 2µS or 20 cycles. In practice there is a sanity check in the program that if the difference is +- 1µS, action is taken to try and force it back to lock within 80 seconds.
There are several arbitary design decisions. The size of the delay was chosen to be smaller than the expected jitter of the 1ppS, but able to track quite large deviations from lock. Also, the program is written so that deviations from lock are compensated - the frequency is adjusted to bring the delay back to the target of 128. It would be possible to program so that if the 1ppS and OCXO were out by 1 instruction time, the program inserted or deleted an instruction time in the timing loop. However if an external device were using the 10MHz output for precise timing of long intervals, this would throw the timing out. Compensating rather than skipping results in slightly larger frequency errors in the short term but an accurate average frequency. Because the delay is varied 1 step of 16nS per second, it can't track the OXCO frequency if it is out by more than 1 cycle in 6 seconds. So it is only useful while the OCXO is close to lock.
Temperature compensation
Charging a capacitor is a necessary step for the programmable delay circuit, so using a thermistor as the resistance and measuring the charge time is a good analog for temperature. The time is measured by TMR1 which counts in 3.2µS intervals. A proportion of the count is used as an offset to the PWM 24-bit value. The proportion is determined by observation - record the calculated PWM and charging times over a long period and see if there is a correlation. Use this as a basis for calculating the offset. This is a simplistic approach but can improve the performance where ambient temperature changes are a problem. Without compensation the output is normally within 1 part in 10^10 of 10MHz. In constant ambient temperature this approaches (and sometimes closer than) 1 part in 10^11.
Determining the frequency
During a measurement period, two values are accumulated; the measured delay, and the delay multiplied by a number 1 through 42. The measurement period is divided into 42 equal subperiods and this provides the number. For longer periods measurements are discarded so the subperiods are all a power of 2 seconds long (e.g if the measurement period is 3 hours or 10800 seconds there are 42 periods of 256 seconds and the last 48 measurements are not used). So the same formula can be used for different measurement periods, the figure is 'adjusted' so it appears that 1024 delays were accumulated in each period (or 43008 in total). The change in delay is calculated using a heavily modified least squares linear interpolation, the formula being:
Delay change =(14*SumXY - 301*Accum)/32
Where Accum is the accumulated delays and SumXY is accumulated delays multiplied by the subperiod.
This yields a number which is close to 2^16 times the change in delay in delay units over the measurement period. The modified formula is used because it takes much less resources than implementing the formula in full, and the result is within a few percent of that from the full formula. The change in delay is usually only a few delay units so for accurate calculations the result should have a fractional part. A 16 bit fraction is used, it is overkill but requires no more resources than an 8-bit fraction. Knowing the measurement period and the delay change allows an estimate of the frequency error. For instance, if the measurement period is 45 minutes and the specification of the GPS unit says the 1ppS is within a microsecond the average of the 2700 samples taken have a measure of uncertainty of (uncertainty of each measurement)/(square root of number of samples) or about 20nS or 0.2Hz. If the calculated drift is an increase of 2 delay times, equates to drift of 2*16nS or about 0.3Hz over 45 minutes. So the frequency was 10MHz - 0.00011Hz uncertainty of plus or minus 0.0008Hz (due to the GPS 1ppS uncertainty). If the control voltage is continually varied, it is much more difficult to do these calculations. Note that there is an assumption that the frequency does not change during the measurement period. There will be some ageing, but over 45 minutes this is small.